The present invention relates to a charge pump circuit for a PLL (Phase Locked Loop) and, more particularly, to a charge pump circuit for a PLL used in an integrated circuit requiring functions such as phasing, frequency multiplication, and clock recovery.
Conventionally, a CMOS IC (Complementary Metal-Oxide Semiconductor Integrated Circuit) requiring functions such as phasing, frequency multiplication, and clock recovery uses a PLL to control the frequency.
FIG. 7 shows the basic arrangement of a general PLL. As shown in FIG. 7, a PLL 1 is constituted by a phase detector (PD) 2, an inverter 3, a charge pump circuit 4, a low-pass filter (LPF) 5, a voltage-controlled oscillator (VCO) 6, and a frequency divider 6a.
The PD 2 compares the phases of a reference clock and an output from the frequency divider 6a. When the phase of an output from the frequency divider lags from the phase of the reference clock, the PD 2 outputs a pulse (to be referred to as a signal UP) for increasing the frequency. When the phase of an output from the frequency divider leads from the phase of the reference clock, the PD 2 outputs a pulse (to be referred to as a signal DN) for decreasing the frequency. As the signal UP, a signal UP inverted by the inverter 3 is used.
The output of the charge pump circuit 4 is connected to the LPF 5 made up of a resistor 5a and a capacitor 5b. The charge pump circuit 4 removes electric charges from the capacitor 5b of the LPF 5 when the charge pump circuit 4 receives the signal DN, and accumulates electric charges in the capacitor 5b of the LPF 5 when the charge pump circuit 4 receives the signal UP. A pulse output from the charge pump circuit 4 is converted into a DC analog signal by the LPF 5.
The VCO 6 receives the analog signal output from the LPF 5 and outputs a constant-frequency signal. The frequency divider 6a is formed from a counter, and divides an output from the VCO 6 into N (N: arbitrary natural number) to supply the divided output to the PD 2.
In the PLL 1, the PD 2, charge pump circuit 4, VCO 6, and frequency divider 6a form one loop, and this loop controls the phases, i.e., frequencies of two input signals to the PD 2 to be equal to each other. The frequency of an output from the VCO 6 is N times the input frequency. By arbitrarily setting the value N, a frequency which is an arbitrary natural multiple of the input frequency can be obtained.
A conventional charge pump circuit will be explained with reference to FIGS. 8A and 8B. As shown in FIGS. 8A and 8B, a power supply VDD is connected to a constant current source 22, and the constant current source 22 is connected to the source of a PMOS transistor 20. Ground is connected to a constant current source 23, and the constant current source 23 is connected to the source of an NMOS transistor 21. The drains of the PMOS and NMOS transistors 20 and 21 are connected to an LPF on the next stage.
FIG. 8A schematically shows the case of supplying the signal UP. That is, when the signal UP is at "L" level, the PMOS transistor 20 serving as an analog switch is turned on to supply a current i.sub.OH to the LPF.
A parasitic capacitance Cfp exists between a node C and the power supply VDD. When the PMOS transistor 20 switches from the OFF state to the ON state, the potential of the source side of the PMOS transistor 20, i.e., the potential of the node C changes from the power supply potential to the filter potential, and a current i.sub.cfp based on the potential difference and Cfp abruptly flows into the LPF.
FIG. 8B schematically shows the case of supplying the signal DN. That is, when the signal DN is at "H" level, the NMOS transistor 21 serving as an analog switch is turned on to flow a current i.sub.OL from the LPF.
A parasitic capacitance Cfn exists between a node D and ground. When the NMOS transistor 21 switches from the OFF state to the ON state, the potential of the source side of the NMOS transistor 21, i.e., the potential of the node D changes from ground potential to the filter potential, and a current i.sub.cfn based on the potential difference and Cfn abruptly flows from the LPF.
As a result, the following problem occurs at the output of the charge pump circuit.
FIG. 9 shows an output current from the charge pump circuit in FIGS. 8A and 8B. As shown in FIG. 9, the currents i.sub.cfp and i.sub.cfn generate overshoots in an output current from the charge pump circuit to cause jitters in the VCO. The phase is permanently repeatedly controlled by an output from the VCO having the jitters, resulting in system errors.
The value of an overshoot current is the product of the potential difference between the potential of the LPF and the power supply voltage by the magnitude of the parasitic capacitance. For this reason, the overshoot can be eliminated by making the potentials of the nodes C and D equal to the potential of the LPF when the transistors 20 and 21 are in the OFF state.
From this viewpoint, the prior art proposed a charge pump circuit like the one shown in FIG. 10.
FIG. 10 shows a conventional charge pump circuit having a function of suppressing an overshoot in an output current. As shown in FIG. 10, CMOS transistors 30 and 31 constituting an analog switch are series-connected between two constant current sources 32 and 33 arranged between the power supply VDD and ground. Each of the CMOS transistors 30 and 31 is made up of a parallel circuit of PMOS and NMOS transistors.
The other terminal of the constant current source 32 having one terminal connected to the power supply VDD is connected to one terminal of a CMOS transistor 34. The other terminal of the constant current source 33 having one terminal connected to ground is connected to one terminal of a CMOS transistor 35.
The connection point between the CMOS transistors 30 and 31 is connected to the non-inverting input terminal of an operational amplifier 36 and the LPF. The output terminal of the operational amplifier 36 is connected to its inverting input terminal, the other terminal of the CMOS transistor 34, and the other terminal of the CMOS transistor 35.
The operational amplifier 36 incorporates a phase compensation capacitor (not shown) for preventing oscillation.
The CMOS transistors 30 and 31 and the CMOS transistors 34 and 35 operate in opposite phases. In other words, while the CMOS transistors 30 and 31 are in the OFF state, the CMOS transistors 34 and 35 are in the ON state. The potentials of the nodes E and G are made equal to the potential of the node F (i.e., the potential of the LPF) by feedback at the operational amplifier 36. Even if the CMOS transistors 30 and 31 are turned on, the potentials of the nodes E and G do not change, and no overshoot is generated in an output current.
However, the capacitor (not shown) in the operational amplifier 36 has a capacitance of about 6 pF. When this charge pump circuit is actually laid out on a chip, the capacitor occupies a large area with respect to the layout area, which interferes with downsizing the chip.